The present invention relates generally to memory cells and, more specifically, to a memory cell having a conductive sill.
In deep sub-micron technology, static-random-access-memory (SRAM) is a very popular storage unit for high-speed, low-power communication devices and other consumer products. As SRAM cells have experienced widespread use, manufacturing costs, thermal stability and power reduction have become important issues. Myriad new procedures and structures have been employed to address these issues.
For example, the “butted” contact (also referred to as a butt contact, a coupled contact or a shared contact) is a widely accepted and utilized process that is employed in memory cell designs to connect a transistor gate and a transistor source/drain region. The butted contact can be generally employed to increase the device density by reducing the amount of area needed for contact purposes. However, the butted contact requires simultaneously etching a standard or square contact and a butted contact, which is often rectangular in shape. This can be very difficult for an etch process to accomplish due to the different contact sizes and shapes and fluctuation of the thicknesses of etch stop layers employed to form the contacts in various polysilicon layers. For example, simultaneously etching two different-shaped contacts can result in a higher junction leakage, possibly attributable to over-etching of an etch stop layer proximate one of the contacts. Current leakage may also occur between a butted contact and an underlying doped well, possibly due to similarities in composition of the doped well and surrounding features, such that the selectivity of an etchant chemistry may not be fully utilized.
Consequently, existing memory devices incorporate additional connectors or interconnects formed in one or more additional conductive layers which, in turn, require additional dielectric layers. Obviously, it is desirable to minimize the number of layers required to fabricate any micro-electronic device, because each additional layer increases manufacturing costs, decreases reliability and product yield, and renders fabrication processes more time consuming and complex. Moreover, the additional connectors and vias required for their interconnection increases the resistance between features interconnected by the additional connectors and vias.
SRAM and other memory cells are also vulnerable to soft error, usually characterized by a quantitative soft error rate (SER). SER is a failure mode that can be caused by ionizing radiation originating from the packaging material or other sources, and can ultimately change the state of a transistor. The significance of SER increases as device geometries continue to shrink.
Accordingly, what is needed in the art is a memory cell and method of manufacture thereof that addresses the above-discussed issues of the prior art.